Design for AI
Engineering the silicon that AI workloads run on, from data centre to edge.
Overview
Three Places AI Silicon Is Being Built
The constraints change completely between a data centre accelerator, a battery-powered edge device and a machine that moves.
Infrastructure AI
Training and inference silicon where performance per watt and memory bandwidth decide the product.
- Datapath and memory subsystems
- High-bandwidth interfaces
- Power and thermal aware RTL
Edge AI
Inference inside a power and area budget, where every milliwatt is argued over.
- Low-power design techniques
- Quantised datapaths
- Always-on subsystems
Physical AI
Silicon for machines that sense and act: robotics, vehicles and industrial systems.
- Sensor fusion pipelines
- Safety-aware verification
- Deterministic latency
Design
RTL for AI accelerators
Datapath, memory hierarchy and interconnect built for throughput.
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Verification
Verifying AI silicon
Coverage models for datapaths that are wide, deep and repetitive.
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Validation
Bring-up and validation
Getting AI silicon running real workloads on real boards.
Learn moreBuilding AI silicon?
We work across infrastructure, edge and physical AI programs.
